MOS silicon gate technology defines an MOS flash memory transistor location by a field oxide opening, and defines the transistor channel location by a polysilicon floating gate overlying this opening, and a polysilicon control gate overlying and aligned to the floating gate. The width of the floating gate determines the channel length L of the transistor, and the width of the field oxide opening determines the channel width W of the transistor. The floating gate length is made longer than the channel width W to allow for misalignment tolerance. For a flash memory transistor with a sub micron channel width this tolerance can be almost as large as the width W. This problem severely limits the layout density of flash memory arrays. As shown in FIG. 1A, the spacing between transistors in the width direction can be no closer than two overlaps 15 plus the spacing 16 between floating gates 12 in the width direction.
Another important concern when designing a flash memory transistor is the coupling capacitance Ccf between the control gate and the floating gate. It is desirable to make Ccf larger than the tunneling capacitance Cfs between the floating gate and the substrate. As shown in FIG. 1B, Ccf is the capacitance between control gate 14 and floating gate 12 separated by dielectric 13, and Cfs is the capacitance between floating gate 12 and the substrate separated by tunneling dielectric 11. As a result of the overlaps 15, It is apparent that the area of control gate 14 is only somewhat larger than the area of floating gate 12. And, since dielectric 11 needs to be very thin for electron tunneling to occur, it is very difficult to make dielectric 13 much thinner than dielectric 11, resulting in Ccf only being somewhat larger than Cfs.